This invention relates to integrated circuits; and more particularly, it relates to methods for fabricating metal interconnections within the circuit.
Basically, an integrated circuit is comprised of a semiconductor substrate having a surface in which a plurality of transistors are fabricated. These transistors are selectively connected by one or more levels of metal conductors which overlie the transistors on respective insulating layers. Metal coated via holes through the insulating layers are used to interconnect different levels of the conductors.
However, a substantial problem with this type of structure is that there is a natural tendency for the metal coating in the via holes to be thinner than the metal conductors which lie on the insulating layers. This decrease in thickness can result in the resistance through the via holes being too high for the circuit to work properly, or it can result in an actual open circuit. Via holes having a high aspect ratio (i.e., a large depth to width ratio) are most susceptible to this problem.
To solve the above described problem, the thickness of the metal coating in the via holes cannot be increased simply by increasing the thickness of the metal conductors on the insulating layers. This is because each conductor is essentially rectangular in cross section, and so it forms a step on the insulating layer on which it lies.
When an insulating layer is deposited over a large step, the thickness of the insulating layer is not uniform. Instead, the insulating layer is thin on the side of the step and this can cause shorts to occur. Also, when a layer of photoresist is deposited over a large step, the resist tends to thin out on the top of the step. This can result in the resist being inadvertently stripped from the top of the step during a subsequent patterning process. Consequently, a dilemma exists wherein increasing the thickness of the metal coating in via holes by depositing more metal aggravates the step coverage problem.
Accordingly, a primary object of the invention is to provide an improved method of fabricating metal interconnections in an integrated circuit which overcomes the above described problem.